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1. Field of the Invention
This invention relates in general to electronic circuits and in particular to de-embedding devices.
2. Description of the Related Art
In the design of integrated circuits such as e.g. high-frequency/RF integrated circuits, it is desired that only the intrinsic characteristics of the underlying semiconductor devices be incorporated in the design process. Typically, determination of the intrinsic characteristics is accomplished in a manner such that unwanted parasitics are introduced into the characterization process, due to the process of fabricating the associated test devices. De-embedding is a process that is utilized to remove the effects of the parasitics from the characteristics of a device under test.
FIGS. 1-4 are functional schematics of 2-port test structures typically used in prior art de-embedding processes. FIG. 1 is a schematic representation of test structure 101 that includes a transmission configured two terminal device under test (DUT) 111, shown as a two-port network. Examples of such devices include capacitors, diodes, inductors, resisters, or any other two terminal device. In one embodiment, DUT 111 is fabricated on a substrate of a semiconductor wafer with input port 103 and output port 107 located on the wafer surface for radio frequency (rf) characterization.
FIG. 2 is a schematic representation of a “thru” test structure typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 201 have the same electrical length and port characteristics as test structure 101 exclusive of DUT 111.
FIG. 3 is a schematic representation of a “short” test structure typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 301 have the same port characteristics and the same electrical length as test structure 101, but with rf “shorts” at locations corresponding to the locations of port-1 and port-2 of DUT 111.
FIG. 4 is a schematic representation of an “open” test structure typically used for de-embedding the electrical characteristics of DUT 111. It is desirable that test structure 401 have the same port characteristics and the same electrical length as test structure 101, but with rf “opens” at locations corresponding to the locations of port-1 and port-2 of DUT 111.
Test structures 201, 301, and 401 are constructed from the same fabrication process as test structure 101 of FIG. 1.
A prior art process of de-embedding typically involves the collection of scattering (S) parameters on test structures 101, 201, 301, and 401. The S parameters from test structure 101 are then modified to remove the effects of parasitics associated with test structure 101 as determined from the S parameters collected from test structures 201, 301, and 401. With some prior art de-embedding processes, test structure 201 may not be required.
The process of de-embedding described above requires the fabrication of three additional test structures (201, 301, and 401). Each additional test structure requires/occupies additional wafer area and increases testing time and complexity. What is desired is an improved process of de-embedding.
The use of the same reference symbols in different drawings indicates identical items unless otherwise noted.